Antifuses are used in a variety of semiconductor circuits for permanently programming digital information. For example, antifuses are often used in semiconductor memory devices, such as synchronous dynamic random access memory (SDRAM), to program the memory addresses of defective memory locations that are remapped to redundant memory locations. Antifuses are also used to permanently set various memory device options or program device information, such as speed grade, data width, and the like. Conventional antifuses are capacitive structures that, in their un-programmed states, form open circuits, and in their programmed states, form short circuits or low resistance circuits. An antifuse may be blown by applying a relatively high-voltage across its two terminals, which causes a dielectric layer disposed between the two terminals to break down, and thus, form a conductive path between the two terminals of the antifuse. Based on the conductivity of the antifuse, a circuit coupled to the antifuse, referred to as an antifuse circuit or an antifuse reading circuit, generates a signal having a logic level that is indicative of the programmed or un-programmed state of the antifuse.
FIG. 1 illustrates a conventional antifuse reading circuit 100 for reading the state of an antifuse 102. The antifuse 102 can be modeled as a capacitor 103 coupled in parallel with a resistance 104 and a switch 105, which are coupled in series. The capacitor 103 with the switch 105 open represents the capacitance of the antifuse 102 in an un-programmed state while the resistance 104 and the switch 105 closed represent the antifuse 102 in a programmed state.
The antifuse 102 has a first node coupled to ground and a second node coupled to a node N1 through an n-channel metal oxide semiconductor (NMOS) transistor 108 having a gate coupled to a pumped voltage VCCP. The VCCP voltage applied to the gate keeps the transistor 108 ON. The node N1 is coupled to an NMOS transistor 110 having a gate coupled to ground. Coupling the gate of the transistor 110 to ground keeps the transistor 110 OFF. The node N1 is coupled to an antifuse state latch 120 through an NMOS transistor 112. A gate of the transistor 112 is coupled to a voltage supply providing a voltage approximately one-half of VCC to keep the transistor 112 in a conductive/resistive state. The transistors 108, 110, and 112 can be used for programming an antifuse, as known in the art. However, as shown in FIG. 1, the antifuse reading circuit 100 is configured for reading the antifuse 102 in response to an active LOW antifuse read signal RDFZf.
The antifuse state latch 120 latches the state of the antifuse 102 in response to the RDFZf signal being pulsed LOW. The antifuse latch 120 includes an activation inverter shown as a p-channel metal oxide semiconductor (PMOS) transistor 130 and an NMOS transistor 134, a first inverter shown as inverter 136, and a second inverter shown as a PMOS transistor 140 and NMOS transistor 148. A latch is formed by the PMOS transistor 140, which is coupled in parallel with the transistor 130, and the NMOS transistor 148, which are both coupled to an output of the inverter 136. A PMOS transistor 144 having a gate coupled to ground provides a voltage VCC for the antifuse latch 120. The PMOS transistor 144 is generally a “long” transistor to provide sufficient current to trigger the antifuse latch 120 during an antifuse read operation when the RDFZf signal is pulsed LOW.
Operation of the antifuse reading circuit 100 will be described with respect to a signal timing diagram illustrated in FIG. 2. The timing diagram generally illustrates a voltage level at a node N2 (FIG. 1) corresponding to an input of the inverter 136 and a voltage level of an output signal OUT provided at the output of the inverter 136 in response to an antifuse read operation initiated by a RDFZf signal 200 being pulsed LOW. The OUT signal has a voltage level that is indicative of the state of the antifuse 102. The N2 signal 202 and the OUT signal 204 correspond to the case when an un-programmed antifuse is read and the N2 signal 206 and the OUT signal 208 correspond to the case when a programmed antifuse is read. At a time T0, prior to the antifuse read operation, the RDFZf signal 200 is HIGH and the OUT signal is HIGH as well. As a result, the transistors 134 and 148 are ON to couple the node N2 to ground, and the transistors 120 and 130 are OFF to isolate the node N2 from the VCC voltage supply. At a time T1, the RDFZf signal is pulsed LOW to initiate the antifuse read operation. In response to the LOW RDFZf signal, the transistor 134 is switched OFF. The transistor 130 is also switched ON to decouple the node N2 from ground and couple the node N2 to the VCC voltage supply, respectively. The OUT signal at this time remains HIGH since the voltage at the node N2 is still less than a voltage trigger level of the inverter 136, at which, the inverter 136 will invert the OUT signal.
In the case where the antifuse 102 is un-programmed, the voltage at the node N2 begins to increase due to the coupling of the VCC voltage supply through the transistor 130. As previously discussed, the un-programmed antifuse 102 can be modeled as the capacitor 103. Thus, the voltage at the node N2 will require a finite time to increase to a voltage level sufficient to cause the inverter 136 to invert the OUT signal. At a time T2, the increasing voltage level of the node N2 is greater than the voltage trigger level of the inverter 136, causing it to invert the OUT signal from HIGH to LOW indicating that the antifuse 102 is un-programmed. The LOW OUT signal switches OFF the transistor 148 and switches ON the transistor 140. As a result, the node N2 is now coupled to the VCC voltage supply through both transistors 130 and 140, and the voltage level of the node N2 increases at a faster rate. The activation of the transistor 140 causes the LOW OUT signal to be latched by coupling the node N2 to the VCC voltage supply. By a time T3, the node N2 is charged to its maximum voltage level, and at a time T4, the RDFZf signal returns HIGH to complete the antifuse read operation by switching the transistor 130 OFF and switching the transistor 134 ON. The LOW OUT signal continues to be latched by the inverter 136 and the transistor 140.
With reference to the N2 signal 206 and the OUT signal 208, in the case where the antifuse 102 is programmed, the voltage level at the node N2 does not increase at the time T1, or increases slightly due to the antifuse 102 being modeled as the resistance 104. That is, when the transistor 130 is switched ON in response to the RDFZf signal being pulsed LOW, the VCC voltage supply is coupled through the transistors 112 and 108, and the programmed antifuse 102 to ground. As a result, the voltage level at the node N2 is never sufficient to cause the inverter 136 to invert the OUT signal, and the OUT signal is maintained LOW at the completion of the antifuse read operation, thus, indicating that the antifuse 102 is programmed.
As illustrated by the previous discussion, the pulse width of the LOW pulse of the RDFZf signal should be sufficient to allow the voltage level of the node N2 to increase to above the voltage trigger level of the inverter 136 in order to accurately read the state of the antifuse 102. Typically, at least 15 nanoseconds (ns) are required to accurately read the state of the antifuse 102 using the conventional antifuse reading circuit 100. If the duration, or “pulse width” of the LOW pulse of the RDFZf signal is not sufficient, an un-programmed antifuse may be incorrectly read as a programmed antifuse. IN order to avoid misreading the state of the antifuse 102, a worst case is assumed and the pulse width of the LOW pulse of the RDFZf signal is typically 30 ns to provide adequate margin.
Under some power, voltage and temperature conditions, however, the pulse width can be as short as 13 ns, less than what is generally required for accurate reading of an antifuse. Moreover, different temperature conditions can also affect the amount of time needed to charge the antifuses due to changes in leakage and junction capacitances. Varying voltage supply levels also influence the amount of time required to charge the antifuse 102. Additionally, physical characteristics of the antifuse 102 and transistors of the antifuse reading circuit may vary substantially between memory devices. For example, the antifuse 102 of one memory device may have substantially greater capacitance than the antifuse 102 in another memory device requiring greater time for the antifuse reading circuit to accurately read the state of an antifuse. Similarly, the transistors in one memory device may offer substantially different resistance to current than the transistors in another memory device due to inherent variations in the processing of large numbers of semiconductor chips. The pulse width of the LOW pulse of the RDFZf signal can be increased to accommodate the various influences to ensure accurate reading of the antifuse state under worst case conditions. However, increasing the pulse width of the LOW pulse of the RDFZf signal will negatively impact power-up performance of the memory device and its operating speed, as well as increase initial power consumption by the memory device.
Therefore, there is a need for an alternative circuit and method for accurately reading the state of an antifuse that is less dependent on the pulse width of a signal initiating an antifuse read operation.